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E2I0012-17-Y1 Semiconductor
Semiconductor MSM51V257CL
32,768-Word 8-Bit CMOS STATIC RAM
This version: Jan. 1998 MSM51V257CL Previous version: Aug. 1996
DESCRIPTION
The MSM51V257CL is a 32,768-word by 8-bit CMOS static RAM featuring 2.7 V to 3.6 V power supply operation and direct LVTTL input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations are unnecessary, making this device very easy to use. The MSM51V257CL, which uses NMOS cells and CMOS peripherals, can be used in highspeed operation at 70 ns access time and in the low current consumption of a standby current max. 24 mA when there is no chip selection. The MSM51V257CL's ability to hold the memory contents at 2 V provides a battery back-up. Since the MSM51V257CL is provided with the CS and OE signals, it can connect with outputs of other chips in a wired OR technique, which provides easy memory expansion and bus line control.
FEATURES
* 32,768-word 8-bit configuration * Power supply voltage: 2.7 V to 3.6 V * Operating temperature range: Ta = 0C to 70C * (Input/Output) LVTTL compatible * 3-state output * Data retention available at power supply voltage 2 V * Package options: 28-pin 600 mil plastic DIP (DIP28-P-600-2.54) (Product : MSM51V257CL-xxRS) 28-pin 430 mil plastic SOP (SOP28-P-430-1.27-K) (Product : MSM51V257CL-xxGS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM51V257CL-70 MSM51V257CL-85 MSM51V257CL-10 Access Time (Max.) 70 ns 85 ns 100 ns Power Dissipation Operating (Max.) 162 mW 144 mW 126 mW 86.4 mW Standby (Max.)
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Semiconductor
MSM51V257CL
PIN CONFIGURATION (TOP VIEW)
A14 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O1 11 I/O2 12 I/O3 13 VSS 14
28 VCC 27 WE 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CS 19 I/O8 18 I/O7 17 I/O6 16 I/O5 15 I/O4 A14 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O1 11 I/O2 12 I/O3 13 VSS 14
28-Pin Plastic DIP
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
28-Pin Plastic SOP
Pin Name A0 - A14 I/O1 - I/O8 CS WE OE VCC, VSS
Function Address Input Data Input/Output Chip Select Write Enable Output Enable Power Supply
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Semiconductor
MSM51V257CL
BLOCK DIAGRAM
A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 Input Data Control Column I/O Circuits Column Select
Row Select
Memory Array 512 Rows 64 Columns 8 Blocks
VCC VSS
A0 A1 A2 A3 A4 A5
CS WE OE
FUNCTION TABLE
Operating Mode Standby Read Cycle Write Cycle CS H L L L WE * H H L OE * H L * Operating Contents Output Floating Output Floating Data Read Data Write
*Don't Care ("H" or "L")
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Semiconductor
MSM51V257CL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power Supply Voltage Pin Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC VT PD Topr Tstg Condition Ta = 25C, for VSS Ta = 25C -- -- Rating -0.5 to 4.6 -0.5* to VCC + 0.5 1.0 0 to 70 -55 to 150 Unit V V W C C
* -1.2 V Min. for pulse width less than 30 ns. Recommended Operating Conditions
Parameter Power Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Load Capacitance Fan Out Symbol VCC VSS VCCH VIH VIL CL N Condition -- -- VCC = 2.7 V to 3.6 V -- LVTTL Min. 2.7 0 2 2.2 -0.3* -- -- Typ. -- 0 -- -- -- -- -- Max. 3.6 0 3.6 VCC + 0.3 0.4 100 1 Unit V V V V V pF --
* -1.2 V Min. for pulse width less than 30 ns. Capacitance
Parameter Input Capacitance Input/Output Capacitance Symbol CI CI/O Condition VI = 0 V VI/O = 0 V Min. -- -- (Ta = 25C, f = 1 MHz) Max. 10 10 Unit pF pF
Note:
This parameter is periodically sampled and not 100% tested.
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Semiconductor
MSM51V257CL
DC Characteristics
Parameter Input Leakage Current Input/Output Leakage Current Output High Voltage Output Low Voltage Standby Power Supply Current Symbol ILI ILO VOH VOL ICCS ICCS1 Condition VI = 0 to VCC CS = VIH or OE = VIH, VI/O = 0 to VCC IOH = -2.0 mA IOL = 2.0 mA CS VCC - 0.2 V, VI = 0 to VCC CS = VIH Min. cycle, IOUT = 0 mA Operating Power Supply Current ICCA f = 1 MHz, VIH VCC - 0.2 V, VIL 0.2 V, IOUT = 0 mA
(VCC = 2.7 V to 3.6 V, Ta = 0C to 70C) MSM51V257CL Min. -1 -1 2.4 -- -- -- -- Typ. -- -- -- -- -- -- -- Max. 1 1 -- 0.4 24 0.6 q Unit mA mA V V mA mA mA
--
--
5
mA
AC Characteristics Test Conditions
Parameter Input Pulse Level Input Rise and Fall Times Input/Output Timing Level Output Load
q 51V257CL-70 45 mA 51V257CL-85 40 mA 51V257CL-10 35 mA
Condition VIH = 2.4 V, VIL = 0.4 V 5 ns 1.4 V CL = 100 pF, 1 LVTTL Gate
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Semiconductor Read Cycle
Parameter Read Cycle Time Address Access Time CS Access Time OE Access Time CS to Output in Low-Z OE to Output in Low-Z Output Hold Time from Address Change CS to Output in High-Z OE to Output in High-Z Symbol tRC tAA tCO tOE tCLZ tOLZ tOH tCHZ
MSM51V257CL
(VCC = 2.7 V to 3.6 V, Ta = 0C to 70C) MSM51V257CL-70 MSM51V257CL-85 MSM51V257CL-10 Min. 70 -- -- -- 5 5 10 -- -- Max. -- 70 70 40 -- -- -- 30 30 Min. 85 -- -- -- 5 5 10 -- -- Max. -- 85 85 45 -- -- -- 30 30 Min. 100 -- -- -- 5 5 10 -- -- Max. -- 100 100 50 -- -- -- 35 35 Unit ns ns ns ns ns ns ns ns ns
A0 - A14
Notes:
, ,,
tOHZ
tRC
tAA
tCO
tCHZ
CS
tOE
tOHZ
OE
tCLZ tOLZ
tOH
I/O
Valid Data-out
1. A read cycle occurs during the overlap of CS = "L", OE = "L" and WE = "H". 2. tCHZ and tOHZ are specified by the time when DATA is floating, not defined by the output level.
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Semiconductor Write Cycle
Parameter Write Cycle Time Address Setup Time Write Pulse Width Write Recovery Time Data Setup Time Data Hold Time WE to Output in High-Z CS to End of Write Address Valid to End of Write Symbol tWC tAS tWP tWR tDS tDH tWHZ tCW tAW
MSM51V257CL
(VCC = 2.7 V to 3.6 V, Ta = 0C to 70C) MSM51V257CL-70 MSM51V257CL-85 MSM51V257CL-10 Min. 70 0 55 5 35 0 -- 65 65 5 Max. -- -- -- -- -- -- 30 -- -- -- Min. 85 0 70 5 40 0 -- 75 75 5 Max. -- -- -- -- -- -- 30 -- -- -- Min. 100 0 75 5 40 0 -- 90 90 5 Max. -- -- -- -- -- -- 35 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns
I/O (DOUT)
, ,,
Output Active from End of Write tWLZ tWC A0 - A14 tWP CS tAW tAS tCW tWR WE tDS tDH I/O (DIN) tWHZ Stable Data-in tWLZ
Notes:
A write cycle occurs during the overlap of CS = "L" and WE = "L". OE may be either of "H" or "L" in the write cycle. tAS is specified from CS = "L" or WE = "L", whichever occurs last. tWP is an overlap time of CS = "L" and WE = "L". tWR, tDS and tDH are specified from CS = "H" or WE = "H", whichever occurs first. tWHZ is specified by the time when DATA output is floating, not defined by the output level. 7. When I/O pins are in the output mode, don't apply the inverted input signal to the output pins. 1. 2. 3. 4. 5. 6.
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Semiconductor Data Retention Characteristics
Parameter Data Retention Power Supply Voltage Data Retention Power Supply Current Chip Deselect to Data Retention Time Operation Recovery Time Symbol VCCH ICCH tCDR tR Condition CS VCC - 0.2 V VCC = 3 V, CS VCC - 0.2 V -- -- Min. 2.0 -- 0 tRC**
MSM51V257CL
(Ta = 0C to 70C) Typ. -- -- -- -- Max. 3.6 20* -- -- Unit V mA ns ns
* 6 mA Max. when Ta = 0C to 40C. ** tRC: Read Cycle Time
tCDR VCC 2.7 V VIH VCCH CS 0V
Data Retention Mode
tR
CS VCC - 0.2 V
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Semiconductor
MSM51V257CL
PACKAGE DIMENSIONS
(Unit : mm)
DIP28-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 4.30 TYP.
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Semiconductor
MSM51V257CL
(Unit : mm)
SOP28-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.75 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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